Current Issue : April - June Volume : 2018 Issue Number : 2 Articles : 5 Articles
3D integration can greatly benefit future many-cores by enabling low-latency three-dimensional Network-on-Chip (3D-NoC)\ntopologies. However, due to high cost, low yield, and frequent failures of Through-Silicon Via (TSV), 3D-NoCs are most likely\nto include only a few vertical connections, resulting in incomplete topologies that pose new challenges in terms of deadlockfree\nrouting and TSV assignment. The routers of such networks require a way to locate the nodes that have vertical connections,\ncommonly known as elevators, and select one of them in order to be able to reach other layers when necessary. In this paper, several\nalternative TSV selection strategies requiring a constant amount of configurable bits per router are introduced. Each proposed\nsolution consists of a configuration algorithm, which provides each router with the necessary information to locate the elevators,\nand a routing algorithm, which uses this information at runtime to route packets to an elevator. Our algorithms are compared by\nsimulation to highlight the advantages and disadvantages of each solution under various scenarios, and hardware synthesis results\ndemonstrate the scalability of the proposed approach and its suitability for cost-oriented designs....
This paper proposes a novel bus encodingmethod onMBUS in order to reduce the power consumption of system-on-chips (SoCs).\nThe main contribution is to lower the bus activity by an average 64.55% and thus decrease the IO power consumption through\nreconfiguring the MBUS transmission. This method is effective because field-programmable gate array (FPGA) IOs are most likely\nto have very large capacitance associated with them and consequently dissipate a lot of dynamic power. Experimental result shows\nan average 70.96% total power reduction compared with the original MBUS implementation....
Recently, we present a novel Mastrovito form of nonrecursive Karatsuba multiplier for all trinomials. Specifically, we found that\nrelated Mastrovito matrix is very simple for equally spaced trinomial (EST) combined with classic Karatsuba algorithm (KA),\nwhich leads to a highly efficient Karatsubamultiplier. In this paper, we consider a new special class of irreducible trinomial, namely,\n...
Synthesis of reversible sequential circuits is a very new research area. It has been shown that such circuits can be implemented\nusing quantum dot cellular automata. Other work has used traditional designs for sequential circuits and replaced the flip-flops\nand the gates with their reversible counterparts. Our earlier work uses a direct feedback method without any flip-flops, improving\nupon the replacement technique in both quantum cost and ancilla inputs.We present here a further improved version of the direct\nfeedback method.Design examples showthat the proposed method produces better results than our earlier method in terms of both\nquantum cost and ancilla inputs.We also propose the first technique for online testing of single line faults in sequential reversible\ncircuits....
Multilevel Cell Spin-Transfer Torque Random Access Memory (MLC STT-RAM) is a promising nonvolatile memory technology\nto build registers for its natural immunity to electromagnetic radiation in rad-hard space environment. Unlike traditional SRAMbased\nregisters, MLC STT-RAM exhibits unbalanced write state transitions due to the fact that the magnetization directions of\nhard and soft domains cannot be flipped independently. This feature leads to nonuniform costs of write states in terms of latency\nand energy. However, current SRAM-targeting register allocations do not have a clear understanding of the impact of the different\nwrite state-transition costs. As a result, those approaches heuristically select variables to be spilled without considering the spilling\npriority imposed by MLC STT-RAM. Aiming to address this limitation, this paper proposes a state-transition-aware spilling cost\nminimization (SSCM) policy, to save power when MLC STT-RAM is employed in register design. Specifically, the spilling cost\nmodel is first constructed according to the linear combination of different state-transition frequencies. Directed by the proposed\ncost model, the compiler picks up spilling candidates to achieve lower power and higher performance. Experimental results show\nthat the proposed SSCM technique can save energy by 19.4% and improve the lifetime by 23.2% of MLC STT-RAM-based register\ndesign....
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